A 16-bit 125 MS/s pipeline analog-to-digital converter (ADC) implemented in a 0.18 ¿m CMOS process is presented in this paper. A SHA-less 4-bit front-end is used to achieve low power and minimize the ...

Datapaths for media signal processing are typically built using programmable computational elements such as adders and multipliers, which can be run-time reconfigured to operate on simple integers ...