Persistent Link: https://ieeexplore.ieee.org/servlet/opac?punumber=4 ...

One is SerDes design. Memory interface designs are getting to faster ... and then you create the next cross-section with the equalization of the DFE (decision feedback equalizer) or CTLE ...

today announced global OEMs and other automotive supply chain vendors have joined the growing ecosystem that is designing products based on the MIPI A-PHY SerDes specification for high-speed image ...

Unfortunately, compensating receiver phase noise after dispersion compensation gives rise to equalization-enhanced phase noise (EEPN), which limits the system's performance, especially for high data ...

The SerDes IP supports data rates from 1.25G to 10.3125Gbps including XFI, SFI, 10GBASE-KR, CEI, XAUI, USXGMII, QSGMII, and SGMII. With the supports for both TX and RX equalization techniques, the ...

OptiCORE includes all of the features of the AlphaCORE electrical SerDes (low-power high-speed ADC, sub-sampling clock multiplier (SSCM), powerful DSP equalization including FFE and DFE, an optional ...

The primary defined application of the XSR SerDes is connecting a chip to a “nearby” optical engine. Because the requirements on these channels are much less stringent than they are on long reach ...