TMSC to show off 20nm chips with FinFET transistors at IEDM. 20nm testing from TMSC - the future of technology? Anthony Garreffa. Gaming Editor. Published Sep 21, 2010 9:32 PM CDT ...

By employing a vertical FinFET GaN transistor design—for higher-voltage, higher-current switches, a vertical structure is preferred since its die area does not depend on the breakdown voltage ...

Imec, the Belgian nanoelectronics research centre has expanded its collaboration with Synopsys in the field of Technology Computer Aided Design (TCAD) for next-generation finfet technology at 10nm.

Cadence Design Systems, Inc. , a leader in global electronic design innovation, announced today the tapeout of a 14-nanometer test-chip featuring an ARM Cortex®-M0 processor implemented using IBM ...

This flexible service leverages Faraday’s ASIC design experiences and resources to support global fabless houses, system houses, ASIC providers, and foundries who access advanced FinFET technology ...

SAN JOSE, Calif., Sept. 11, 2017 /PRNewswire/ -- Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced its collaboration with TSMC to advance 7nm FinFET Plus design innovation for mobile and ...

FinFET processes are making it possible to reintroduce an aggressive low-energy circuit design technique that shortcomings in planar processes had made unattractive. A University of Michigan (UM) team ...

Qualification includes leading products Design Compiler NXT, IC Compiler II, StarRC, PrimeTime, and IC Validator Collaboration delivers a combination of accuracy and highest performance with ...