FinFET prototypes have been fabricated using an aluminium hard mask FIB milling technique for fin definition and SiON/TiN/Al gate stack. A three dimensional fin with sub-100nm dimensions was obtained.

This brief introduces an energy-efficient 10-bit 500-MS/s pipelined SAR ADC that uses feedback factor compensation in 6-nm FinFET technology. The design challenges of residue amplifier in FinFET ...

Employing more stress testing at the wafer level improves quality while reducing burn-in time and cost. So why isn’t it ...

In Part 1, we explored the challenges of implementing machine learning and real-time analytics in semiconductor ...