FinFET prototypes have been fabricated using an aluminium hard mask FIB milling technique for fin definition and SiON/TiN/Al gate stack. A three dimensional fin with sub-100nm dimensions was obtained.

Employing more stress testing at the wafer level improves quality while reducing burn-in time and cost. So why isn’t it ...

In this work, we demonstrate the use of a bulk FinFET designed in a 12-nm CMOS technology node, as a quantum dot (QD)-based thermometer at cryogenic temperatures. Although the operational principles ...