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IEEE1d
A 4-GS/s 11.3-mW 7-bit Time-Based ADC With Folding Voltage-to-Time Converter and Pipelined TDC in 65-nm CMOS - IEEE Xplore
A 7-bit TB ADC is implemented with a 4× folding VTC having a 2-bit digital output and a 5-bit pipelined TDC for high-speed low-power operation. A TB ADC fabricated in a 1-V 65-nm CMOS process achieves ...
IEEE6d
A Deep Learning Approach for Active S-Box Prediction of Lightweight Generalized Feistel Block Ciphers - IEEE Xplore
One of the main security requirements for symmetric-key block ciphers is resistance against differential cryptanalysis. This is commonly assessed by counting the number of active substitution boxes (S ...