This work investigates the reliability and aging predictions in a 14-nm FinFET-based analog circuit under high-temperature conditions. Aging simulations and accelerated aging tests were carried out on ...

Employing more stress testing at the wafer level improves quality while reducing burn-in time and cost. So why isn’t it ...

Fin height and width dependence of negative and positive Bias Temperature Instability (N/PBTI) on logic for memory high-κ metal gate (HKMG) FinFET transistors is reported for the first time. It was ...